An ultra-low-power CMOS voltage reference generator based on body bias technique

被引:27
|
作者
Zeng, Yanhan [1 ]
Huang, Yirong [1 ]
Luo, Yunling [1 ]
Tan, Hong-Zhou [1 ]
机构
[1] Sun Yat Sen Univ, Sch Informat Sci & Technol, Guangzhou 510006, Guangdong, Peoples R China
基金
中国国家自然科学基金;
关键词
CMOS voltage reference; Temperature compensation; Body bias technique; Lower power; Analog circuit; PPM/DEGREES-C; IMPACT;
D O I
10.1016/j.mejo.2013.07.003
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18 mu m CMOS technology in this paper. The proposed circuit can achieve a temperature coefficient of 19.4 ppm/degrees C in a temperature range from -20 degrees C to 80 degrees C, and a line sensitivity of 0.024 mV/V in a supply voltage range from 0.85 V to 2.5 V, without the use of resistors and any other special devices such as thick gate oxides MOSFETs with higher threshold voltage. The supply current at the maximum supply voltage and at 27 degrees C is 214 nA. The power supply rejection ratio without any filtering capacitor at 10 Hz and 10 kHz are -88.2 dB and -36 dB, respectively. (C) 2013 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1145 / 1153
页数:9
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