Implementation of DNN on a RISC-V Open Source Microprocessor for IoT devices

被引：0

作者：

Cai, Jingyong ^{[1
]}

Takemoto, Masashi ^{[2
]}

Nakajo, Hironori ^{[3
]}

机构：

[1] Tokyo Univ Agr & Technol, Grad Sch Engn, Tokyo, Japan

[2] BeatCraft Inc, Tokyo, Japan

[3] Tokyo Univ Agr & Technol, Inst Engn, Tokyo, Japan

来源：

2018 IEEE 7TH GLOBAL CONFERENCE ON CONSUMER ELECTRONICS (GCCE 2018) | 2018年

关键词：

Feature Extraction; RISC-V; Logarithmic Quantization; DNN;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Logarithmic Quantization[1] and feature extraction enable us to reduce model parameters to a great extent. Based on these methods, we have implemented a small sized DNN on a RISC-V microprocessor with RAM of only 16KB. We also propose a feature extraction algorithm which outperforms the original fully connected neural network and reduces inputs by 12.25x at the same time. MNIST[2] dataset is used as our training samples and Chainer[8] is used to train the network. As the result, we reduced weights size by nearly 86x from 49.625KB to 0.578KB which make it possible to store these weights in arrays and load them directly into the RAM.

引用

下载

页码：295 / 299

页数：5

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