3D Die Level Packaging for Hybrid Systems

被引：0
|
作者：
Krishna, N. P. Vamsi [1 ]
Sen, Prosenjit [1 ]
机构：
[1] Indian Inst Sci, Ctr Nano Sci & Engn, Bangalore, Karnataka, India
来源：
2016 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE / ADVANCED METALLIZATION CONFERENCE (IITC/AMC) | 2016年
关键词：
3D stacking; ultrathin chip package (UTCP); Integration; MEMS; MOS; die stacking;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The aim of this work is to develop and optimize processing technologies required for 3-D die level packaging of hybrid systems including MEMS and MOS components. In this paper we report the process development for stacking of ultra-thin silicon dies (as low as 10 mu m) and a basic 5 mu m thick MEMS device (Cantilever). SU-8 has been used as the patternable dielectric filler between the device layers.
引用
收藏
页码：120 / 122
页数：3
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