Modeling, Simulation and Implementation of a Passive Mixer in 130nm CMOS Technology and Scaling Issues for Future Technologies

被引:4
|
作者
Komoni, Krenar [1 ]
Sonkusale, Sameer [1 ]
机构
[1] Tufts Univ, Dept Elect & Comp Engn, Medford, MA 02155 USA
关键词
D O I
10.1109/MWSCAS.2008.4616823
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, modeling, simulation, and implementation of double-balanced passive mixer are shown and examined. We analyze the performance of the mixer in terms of conversion gain (Gc), 1-dB compression point, and Noise Figure (NF). We will show the accuracy of our model and analyses when compared with simulation and measured results for a 130nm technology based mixer design. We introduce a mixer's figure-of-merit (FOMMIXER) and briefly show that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance.
引用
收藏
页码:410 / 413
页数:4
相关论文
共 50 条
  • [1] Design of Passive UHF RFID Tag in 130nm CMOS Technology
    Hong, Yang
    Chan, Chi Fat
    Guo, Jianping
    Ng, Yuen Sum
    Shi, Weiwei
    Leung, Lai Kan
    Leung, Ka Nang
    Choy, Chiu Sing
    Pun, Kong Pang
    [J]. 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 1371 - 1374
  • [2] Implementation of CMOS Charge Sharing Dynamic Latch Comparator in 130nm and 90nm Technologies
    Kapadia, Dhanisha N.
    Gandhi, Priyesh P.
    [J]. 2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES (ICT 2013), 2013, : 16 - 20
  • [3] Low-Leakage ESD Structures in 130nm CMOS Technology
    Nagy, Lukas
    Chvala, Ales
    Stopjakova, Viera
    [J]. PROCEEDINGS OF THE 2020 30TH INTERNATIONAL CONFERENCE RADIOELEKTRONIKA (RADIOELEKTRONIKA), 2020, : 177 - 180
  • [4] Accurate gate CD control for 130nm CMOS technology node
    Nagase, M
    Yokota, K
    Mituiki, A
    Tokashiki, K
    [J]. 2003 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS, 2003, : 183 - 186
  • [5] Statistical characterization of hold time violations in 130nm CMOS technology
    Neuberger, Gustavo
    Kastensmidt, Femanda
    Reis, Ricardo
    Wirth, Gilson
    Brederlow, Ralf
    Pacha, Christian
    [J]. ESSCIRC 2006: PROCEEDINGS OF THE 32ND EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2006, : 114 - +
  • [6] Integrated 130 nm CMOS passive mixer for 5 GHz WLAN applications
    Circa, R
    Pienkowski, D
    Boeck, G
    [J]. 2005 SBMO/IEEE MTT-S INTERNATIONAL MICROWAVE AND OPTOELECTRONICS CONFERENCE (IMOC), 2005, : 101 - 104
  • [7] Benchmarking of advanced CD-SEMs at the 130nm CMOS technology node
    Bunday, BD
    Bishop, M
    [J]. METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XVI, PTS 1 & 2, 2002, 4689 : 102 - 115
  • [8] Development of a 20 GS/s Sampler Chip in 130nm CMOS Technology
    Bogdan, Mircea
    Frisch, Henry J.
    Genat, Jean-Francois C.
    Grabas, Herve
    Heintz, Mary K.
    Meehan, Samuel
    Oberla, Eric
    Ruckman, Larry L.
    Tang, Fukun
    Varner, Gary S.
    [J]. 2009 IEEE NUCLEAR SCIENCE SYMPOSIUM CONFERENCE RECORD, VOLS 1-5, 2009, : 1929 - +
  • [9] Modeling and Design of a Dual-Residue Pipelined ADC in 130nm CMOS
    Steen-Hansen, Eirik
    Ytterdal, Trond
    [J]. 2012 NORCHIP, 2012,
  • [10] A Fully-integrated Optical Duobinary Transceiver in a 130nm SOI CMOS Technology
    Buckwalter, James F.
    Kim, Joohwa
    Zheng, Xuezhe
    Li, Guoliang
    Raj, Kannan
    Krishnamoorthy, Ashok
    [J]. 2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2011,