FPGA BASED IMPLEMENTATION OF A FUZZY NEURAL NETWORK MODULAR ARCHITECTURE FOR EMBEDDED SYSTEMS

被引:0
|
作者
Prado, R. N. A. [1 ]
Melo, J. D. [1 ]
Oliveira, J. A. N. [1 ]
Doria Neto, A. D. [1 ]
机构
[1] Univ Fed Rio Grande do Norte, Post Grad Program Elect & Computat Engn, BR-59072970 Natal, RN, Brazil
关键词
Fuzzy Neural Network; Takagi Hayashi method; neural network driven fuzzy reasoning; hybrid systems; DSPBuilder (R); Modular Architecture; FPGA;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
This paper presents a FPGA based approach for a modular architecture of Fuzzy Neural Networks (FNN) to embed with easily different topologies set up. The project is based on a Takagi - Hayashi (T-H) method for the construction and tuning of fuzzy rules, this is commonly referred as neural network driven fuzzy reasoning. The proposed architecture approach consists of two main configurable modules: a Multilayer Perceptron - MLP with sigmoidal activation function that composes the first module to determine a Fuzzy membership function; the second employs an MLP with pure linear activation function to define the consequents. The DSPBuilder (R) software along the Simulink (R) is used to connect, set and synthesize the Fuzzy Neural Network desired. Other hardware components employed in the architecture proposed cooperate to the system modularity. The system was tested and validated through a control problem and an interpolation problem. Several papers proposed different hardware architecture to implement hybrid systems by using Fuzzy logic and Neural Network. However, there is no approach with this specific neural network driven fuzzy reasoning by T-H method and the aim to be embedded. The Self-Organizing Map (SOM) and Levenberg-Marquardt backpropagation were used to train the FNN proposed off-line.
引用
收藏
页数:7
相关论文
共 50 条
  • [1] THE IMPLEMENTATION OF SPEECH RECOGNITION SYSTEMS ON FPGA-BASED EMBEDDED SYSTEMS WITH SOC ARCHITECTURE
    Pan, Shing-Tai
    Lai, Chih-Chin
    Tsai, Bo-Yu
    [J]. INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL, 2011, 7 (11): : 6161 - 6175
  • [2] A Hybrid Architecture for Efficient FPGA-based Implementation of Multilayer Neural Network
    Lin, Zhen
    Dong, Yiping
    Li, Yan
    Watanabe, Takahiro
    [J]. PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS), 2010, : 616 - 619
  • [3] Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network
    Pande, Sandeep
    Morgan, Fearghal
    Cawley, Seamus
    Bruintjes, Tom
    Smit, Gerard
    McGinley, Brian
    Carrillo, Snaider
    Harkin, Jim
    McDaid, Liam
    [J]. NEURAL PROCESSING LETTERS, 2013, 38 (02) : 131 - 153
  • [4] Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network
    Sandeep Pande
    Fearghal Morgan
    Seamus Cawley
    Tom Bruintjes
    Gerard Smit
    Brian McGinley
    Snaider Carrillo
    Jim Harkin
    Liam McDaid
    [J]. Neural Processing Letters, 2013, 38 : 131 - 153
  • [5] Auditory perception architecture with spiking neural network and implementation on FPGA
    Deng, Bin
    Fan, Yanrong
    Wang, Jiang
    Yang, Shuangming
    [J]. NEURAL NETWORKS, 2023, 165 : 31 - 42
  • [6] Scalable FPGA-Based Convolutional Neural Network Accelerator for Embedded Systems
    Zhao, Jingyuan
    Yin, Zhendong
    Zhao, Yanlong
    Wu, Mingyang
    Xu, Mingdong
    [J]. 2019 4TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND APPLICATIONS (ICCIA 2019), 2019, : 36 - 40
  • [7] Implementation architecture for group network profile in embedded systems
    Lin, H
    Gao, Q
    Ye, DX
    [J]. APOC 2001: ASIA-PACIFIC OPTICAL AND WIRELESS COMMUNICATIONS: WIRELESS AND MOBILE COMMUNICATIONS, 2001, 4586 : 226 - 235
  • [8] A Single Layer Architecture to FPGA Implementation of BP Artificial Neural Network
    Liu Shoushan
    Chen Yan
    Xu Wenshang
    Zhang Tongjun
    [J]. 2010 2ND INTERNATIONAL ASIA CONFERENCE ON INFORMATICS IN CONTROL, AUTOMATION AND ROBOTICS (CAR 2010), VOL 2, 2010, : 258 - 264
  • [9] Neural network implementation on a FPGA
    Chen, YJ
    du Plessis, WP
    [J]. 2002 IEEE AFRICON, VOLS 1 AND 2: ELECTROTECHNOLOGICAL SERVICES FOR AFRICA, 2002, : 337 - 342
  • [10] A neural network FPGA implementation
    Coric, S
    Latinovic, I
    Pavasovic, A
    [J]. NEUREL 2000: PROCEEDINGS OF THE 5TH SEMINAR ON NEURAL NETWORK APPLICATIONS IN ELECTRICAL ENGINEERING, 2000, : 117 - 120