Customized NoC Topologies Construction for High Performance Communication Architectures

Different Intellectual Property (IP) cores, including processor and memory, are interconnected to build a typical System-on-Chip(SoC) architectures. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip (NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale Systems-on-Chip (SoC) design. Hence to improve the performance of SoC, first we did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, we observed that the overall latency and throughput of the EBFT is better compared to other topologies. Our next objective is to generate an area and power optimized NoC topology, for this purpose we used Rectilinear-Steiner-Tree (RST)-based algorithms for generating efficient and optimized network topologies. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieve reduction in power consumption and average hop count over custom topology implementation.