Performance and communication energy constrained embedded benchmark for fault tolerant core mapping onto NoC architectures

被引:0
|
作者
Kumar, Aruru Sai [1 ]
Rao, T. V. K. Hanumantha [1 ]
Reddy, B. Naresh Kumar [2 ]
机构
[1] Natl Inst Technol, Dept Elect & Commun Engn, Warangal, Andhra Pradesh, India
[2] Digital Univ Kerala IIITM Kerala, Sch Elect Syst & Automat, Trivendrum, India
关键词
system-on-chip; SoC; network-on-chip; NoC; core; core mapping; core failure; fault tolerance; FT; multimedia benchmarks; communication energy; system performance; execution time; MESH-BASED NETWORK; RELIABILITY; AWARE;
D O I
10.1504/IJAHUC.2022.125427
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Due to the rapid growth of the components encapsulated on the on-chip architecture, the performance degradation and communication issues between the cores significantly impact NoC architecture. It also increases the possibility of core failures encountered in an application, leading to a faulty network. This research implemented fault-tolerant mapping algorithm (FTMAP) that focuses predominantly on replacing the faulty cores and assessing the communication and the execution time of the network by employing it on various multimedia benchmarks. The experimental outcomes reveal that it reduces the communication energy by 8%, 12%, 14% with respect to NFT, 1FT, 2FT compared to FTTG and 6%, 9%, 10% with respect to NFT, 1FT, 2FT when compared to K-FTTG. The reduction of the execution time has also outperformed by 18%, 24%, 26% with respect to NFT, 1FT, 2FT compared to FTTG and 13%, 19%, 21% with respect to NFT, 1FT, 2FT when compared to K-FTTG.
引用
收藏
页码:108 / 117
页数:11
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