A 10-bit Asynchronous SAR ADC with Scalable Conversion Time in 0.18μm CMOS

被引：0
|
作者：
Tung, Po-Chiang
Fan, Duen-Ting
Tsai, Tsung-Heng [1 ]
机构：
[1] Natl Chung Cheng Univ, Dept Elect Engn, Chiayi, Taiwan
来源：
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2016年
关键词：
Metastability; Low power; Low voltage; SAR ADC; Asynchronous;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a 10b 100-to-500 kS/s asynchronous SAR ADC is proposed and prototyped in 0.18 mu m CMOS. The supply voltage is scaled down appropriately for different sampling speeds to minimize the power consumption. At a 0.5-V supply voltage and a 100 kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 56.35 dB and consumes 424 nW, resulting in a figure of merit of 7.9 fJ/conversion-step. The ADC core occupies an active area of only 0.077 mm(2).
引用
收藏
页码：1454 / 1457
页数：4
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