Self-aligned Double Patterning Compliant Routing with In-Design Physical Verification Flow

被引:2
|
作者
Gao, Jhih-Rong [1 ]
Jawandha, Harshdeep
Atkar, Prasad
Walimbe, Atul
Baidya, Bikram
Rizzo, Olivier
Pan, David Z. [1 ]
机构
[1] Univ Texas Austin, ECE Dept, Austin, TX 78712 USA
关键词
D O I
10.1117/12.2013245
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Among double patterning techniques, Self-aligned double patterning (SADP) has the advantage of good mask overlay control, which has made SADP a popular double patterning method for sub-32nm technology nodes. However, SADP process places several limitations on design flexibility. This work exploits an alternative post routing approach that has the flexibility to resolve lithography violations without the overhead of repeated rule checking. In addition, it allows for successive refinement in the definition of lithographic violations as the process node matures, and implementation of fixes as localized ECO (Engineering Change Order) operations without needing to reroute the complete design.
引用
收藏
页数:9
相关论文
共 50 条
  • [41] Mask Cost Reduction with Circuit Performance Consideration for Self-Aligned Double Patterning
    Zhang, Hongbo
    Du, Yuelin
    Wong, Martin D. F.
    Chao, Kai-Yuan
    2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2011,
  • [42] A Polynomial Time Exact Algorithm for Self-Aligned Double Patterning Layout Decomposition
    Xiao, Zigang
    Du, Yuelin
    Zhang, Hongbo
    Wong, Martin D. F.
    ISPD 12: PROCEEDINGS OF THE 2012 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN, 2012, : 17 - 24
  • [43] A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning
    Ihara, Takeshi
    Hongo, Toshiyuki
    Takahashi, Atsushi
    Kodama, Chikaaki
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2017, E100A (07) : 1473 - 1480
  • [44] Overlay-aware Layout Legalization for Self-Aligned Double Patterning Lithography
    Huang, Chong-Meng
    Fang, Shao-Yun
    2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2016,
  • [45] Layout Decomposition for Spacer-is-Metal (SIM) Self-Aligned Double Patterning
    Fang, Shao-Yun
    Tai, Yi-Shu
    Chang, Yao-Wen
    2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2015, : 671 - 676
  • [46] Self-Aligned Double Patterning Decomposition for Overlay Minimization and Hot Spot Detection
    Zhang, Hongbo
    Du, Yuelin
    Wong, Martin D. F.
    Topaloglu, Rasit
    PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, : 71 - 76
  • [47] Defect Gallery and Bump Defect Reduction in the Self-Aligned Double Patterning Module
    Cai, Cathy
    Padhi, Deenesh
    Seamons, Martin
    Bencher, Chris
    Ngai, Chris
    Kim, Bok Heon
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2011, 24 (02) : 145 - 150
  • [48] Effective Two-Dimensional Pattern Generation for Self-Aligned Double Patterning
    Ihara, Takeshi
    Takahashi, Atsushi
    Kodama, Chikaaki
    2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2015, : 2141 - 2144
  • [49] Integrated in situ self-aligned double patterning process with fluorocarbon as spacer layer
    Chang, Bingdong
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2020, 38 (03):
  • [50] Process variability of self-aligned multiple patterning
    Oyama, Kenichi
    Yamauchi, Shohei
    Hara, Arisa
    Natori, Sakurako
    Yaegashi, Hidetami
    ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY XXX, 2013, 8682