共 50 条
- [21] Protection of layout designs (topographies) of integrated circuits - RIP? IIC-INTERNATIONAL REVIEW OF INDUSTRIAL PROPERTY AND COPYRIGHT LAW, 2001, 32 (06): : 648 - 658
- [23] COMPUTER-AIDED LAYOUT SYSTEM FOR INTEGRATED CIRCUITS IEEE TRANSACTIONS ON CIRCUIT THEORY, 1971, CT18 (01): : 128 - &
- [27] Implementation of space-efficient voltage-insensitive capacitances in integrated circuits 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 1876 - 1879
- [29] APPLICATION OF LUMPED ELEMENT TECHNIQUES TO HIGH-FREQUENCY HYBRID INTEGRATED-CIRCUITS RADIO AND ELECTRONIC ENGINEER, 1974, 44 (08): : 414 - 420
- [30] A Hierarchical Layout Generation Method for Quantum Circuits 2013 17TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS 2013), 2013, : 51 - 57