Analog/RF performance of source-side only dual-k sidewall spacer trigate junctionless transistor with parametric variations

In this paper, analog/RE performance of source side only dual-k spacer (Dual-kS) trigate junctionless transistor (JLT) is investigated with respect to the parametric variations. It is observed that the Dual-kS JLT improves analog/RF figure of merits (FOMs) and shows its lower dependence to the parametric variations compared with the conventional (low-k spacer) JLT. This study reveals that the design of Dual-kS JLT with lower aspect ratio (1-3) improves the analog FOMs with moderate frequency of operations at fin-width of 10 nm with gate length being 20 nm. Moreover, the frequency of operation can be increased further by increasing the aspect ratio (4-6) without sacrificing the analog FOMs such as transconductance (g(m)), output conductance (g(ds)) and intrinsic voltage gain (A(V0)). It is also reported that g(ds) of Dual-kS JLT is least sensitive to the variation in fin-width, doping concentration and oxide thickness, which proves the potential of Dual-kS device to act as a constant current source. Moreover, Dual-kS device is found to be robust against the variation in doping concentration and oxide thickness, which further improves the merit of Dual-kS JLT for low-voltage/low-power analog/RE applications. (C) 2016 Elsevier Ltd. All rights reserved.