An Efficient Synthesis Method for Ternary Reversible Logic

被引:0
|
作者
Basu, Saikat [1 ]
Mandal, Sudhindu Bikash [2 ]
Chakrabarti, Amlan [2 ]
Sur-Kolay, Susmita [1 ]
机构
[1] Indian Stat Inst, Adv Comp & Microelect Unit, Kolkata, India
[2] Univ Calcutta, AK Choudhury Sch IT, Kolkata, India
关键词
Degree of adjacency; Prime implicants; Projection Operators; Muthukrishnan-Stroud gates; MINIMIZATION;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
While the role of ternary reversible and quantum computation has been growing, synthesis methodologies for such logic, have been addressed in only a few works. A reversible ternary logic function can be expressed as minterms by using projection operators. In this paper, a novel realization of the projection operators using a minimum number of permutative ternary Muthukrishnan-Stroud (M-S) gates is presented. Next, an efficient method for logic simplification for ternary reversible logic is proposed. This method along with the new construction of projection operators yields significantly lower gate cost of approximately 31% less than that obtained by earlier methodologies, for the synthesis of ternary benchmark circuits.
引用
收藏
页码:2306 / 2309
页数:4
相关论文
共 50 条
  • [41] Ternary Galois field expansions for reversible logic and Kronecker decision diagrams for ternary GFSOP minimization
    Khan, MHA
    Perkowski, MA
    Khan, MR
    34TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2004, : 58 - 67
  • [42] Exact Synthesis of Ternary Reversible Functions using Ternary Toffoli Gates
    Kole, Abhoy
    Rani, P. Mercy Nesa
    Datta, Kamalika
    Sengupta, Indranil
    Drechsler, Rolf
    2017 IEEE 47TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2017), 2017, : 179 - 184
  • [43] Ternary Max-Min Algebra for Representation of Reversible Logic Functions
    Khan, Musharrat
    Rice, Jacqueline E.
    2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 1670 - 1673
  • [44] Design and Implementation of Reversible Logic Based Ternary Content Addressable Memory
    Santhi, C.
    Babu, Moparthy Gurunadha
    SMART INTELLIGENT COMPUTING AND APPLICATIONS, VOL 2, 2020, 160 : 405 - 413
  • [45] A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells
    Zarandi, Arezoo Dabaghi
    Reshadinezhad, Mohammad Reza
    Rubio, Antonio
    IEEE ACCESS, 2020, 8 : 58585 - 58593
  • [46] Efficient three variables reversible logic synthesis using mixed-polarity Toffoli gate
    Cheng, Chua Shin
    Singh, Ashutosh Kumar
    Gopal, Lenin
    PROCEEDINGS OF THE 4TH INTERNATIONAL CONFERENCE ON ECO-FRIENDLY COMPUTING AND COMMUNICATION SYSTEMS, 2015, 70 : 362 - 368
  • [47] An Efficient Design for Testability Approach of Reversible Logic Circuits
    Mondal, Joyati
    Deb, Arighna
    Das, Debesh K.
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2021, 30 (06)
  • [48] Efficient Simulation-based Debugging of Reversible Logic
    Frehse, Stefan
    Wille, Robert
    Drechsler, Rolf
    40TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC ISMVL 2010, 2010, : 156 - 161
  • [49] GFSOP Based Ternary Quantum Logic Synthesis
    Khan, Mozammel H. A.
    OPTICS AND PHOTONICS FOR INFORMATION PROCESSING IV, 2010, 7797
  • [50] An Efficient Design of Graycode Circuit Using Reversible Logic
    Moon, Seo Yeon
    Park, Jong Hyuk
    ADVANCED SCIENCE LETTERS, 2016, 22 (09) : 2607 - 2608