An Efficient Synthesis Method for Ternary Reversible Logic

被引:0
|
作者
Basu, Saikat [1 ]
Mandal, Sudhindu Bikash [2 ]
Chakrabarti, Amlan [2 ]
Sur-Kolay, Susmita [1 ]
机构
[1] Indian Stat Inst, Adv Comp & Microelect Unit, Kolkata, India
[2] Univ Calcutta, AK Choudhury Sch IT, Kolkata, India
关键词
Degree of adjacency; Prime implicants; Projection Operators; Muthukrishnan-Stroud gates; MINIMIZATION;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
While the role of ternary reversible and quantum computation has been growing, synthesis methodologies for such logic, have been addressed in only a few works. A reversible ternary logic function can be expressed as minterms by using projection operators. In this paper, a novel realization of the projection operators using a minimum number of permutative ternary Muthukrishnan-Stroud (M-S) gates is presented. Next, an efficient method for logic simplification for ternary reversible logic is proposed. This method along with the new construction of projection operators yields significantly lower gate cost of approximately 31% less than that obtained by earlier methodologies, for the synthesis of ternary benchmark circuits.
引用
收藏
页码:2306 / 2309
页数:4
相关论文
共 50 条
  • [1] Synthesis of Balanced Ternary Reversible Logic Circuit
    Mondal, Bikromadittya
    Sarkar, Pradyut
    Saha, Pranay Kumar
    Chakraborty, Susanta
    2013 IEEE 43RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2013), 2013, : 334 - 339
  • [2] Synthesis of Ternary Non-Reversible Logic Circuits
    Li, Xiaoyu
    Yang, Guowu
    Zheng, Desheng
    2010 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION (CEC), 2010,
  • [3] A synthesis method for MVL reversible logic
    Miller, DM
    Dueck, GW
    Maslov, D
    34TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2004, : 74 - 80
  • [4] Ternary reversible logic synthesis algorithm with minimum chaos degree
    Xu, Ming-Qiang
    Guan, Zhi-Jin
    Zhang, Hai-Bao
    Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2013, 41 (07): : 1352 - 1357
  • [5] Improved Ternary Reversible Logic Synthesis Using Group Theoretic Approach
    Rani, P. Mercy Nesa
    Datta, Kamalika
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2020, 29 (12)
  • [6] Efficient Reversible Logic Synthesis via Isomorphic Subgraph Matching
    Krishna, Mridul
    Chattopadhyay, Anupam
    2014 IEEE 44TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2014), 2014, : 103 - 108
  • [7] Synthesis of Reversible Logic Functions using Ternary Max-Min Algebra
    Khan, Musharrat
    Rice, Jacqueline E.
    2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 1674 - 1677
  • [8] Synthesis of reversible logic
    Agrawal, A
    Jha, NK
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 1384 - 1385
  • [9] A Review on Fundamentals of Ternary Reversible Logic Circuits
    Rani, P. Mercy Nesa
    Thangkhiew, Phrangboklang Lyngton
    2020 INTERNATIONAL CONFERENCE ON COMPUTATIONAL PERFORMANCE EVALUATION (COMPE-2020), 2020, : 738 - 743
  • [10] Study on a reversible ternary logic cellular array
    Han, Shu
    Tien Tzu Hsueh Pao/Acta Electronica Sinica, 1994, 22 (02): : 107 - 108