共 50 条
- [1] Synthesis of Balanced Ternary Reversible Logic Circuit 2013 IEEE 43RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2013), 2013, : 334 - 339
- [2] Synthesis of Ternary Non-Reversible Logic Circuits 2010 IEEE CONGRESS ON EVOLUTIONARY COMPUTATION (CEC), 2010,
- [3] A synthesis method for MVL reversible logic 34TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2004, : 74 - 80
- [4] Ternary reversible logic synthesis algorithm with minimum chaos degree Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2013, 41 (07): : 1352 - 1357
- [6] Efficient Reversible Logic Synthesis via Isomorphic Subgraph Matching 2014 IEEE 44TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2014), 2014, : 103 - 108
- [7] Synthesis of Reversible Logic Functions using Ternary Max-Min Algebra 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 1674 - 1677
- [8] Synthesis of reversible logic DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 1384 - 1385
- [9] A Review on Fundamentals of Ternary Reversible Logic Circuits 2020 INTERNATIONAL CONFERENCE ON COMPUTATIONAL PERFORMANCE EVALUATION (COMPE-2020), 2020, : 738 - 743
- [10] Study on a reversible ternary logic cellular array Tien Tzu Hsueh Pao/Acta Electronica Sinica, 1994, 22 (02): : 107 - 108