Development of Chip-First and Die-up Fan-out Wafer Level Packaging

被引：0

作者：

Hua, Xuan ^{[1
]}

Xu, Hong ^{[1
]}

Zhang, Li ^{[1
]}

Chen, Dong ^{[1
]}

Tan, K. H. ^{[1
]}

Lai, C. M. ^{[1
]}

Lau, John ^{[2
]}

Li, Ming ^{[2
]}

Li, Margie ^{[2
]}

Kuah, Eric ^{[2
]}

Fan, Nelson ^{[2
]}

Kai, Wu ^{[2
]}

Cheung, Ken ^{[2
]}

机构：

[1] Jiangyin Changdian Adv Packaging Co LTD, 275 Binjiang Middle Rd, Jiangyin, Jiangsu, Peoples R China

[2] ASM Pacific Technol, 16-22 Kung Yip St, Kwai Chung, Hong Kong, Peoples R China

来源：

2017 IEEE 19TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This study is for fan-out wafer-level packaging (FOWLP) with chip-first and die-up processing. The chips with Cu contact pads on the front-side and a die attach film on the backside are picked and placed face-up on a temporary glass carrier with a layer of light-to-heat conversion material. It is followed by compression molding with epoxy molding compound (EMC) and post mold cure (PMC) on the reconstituted wafer carrier, and then backgrinding the molded EMC to expose the Cu contact pads (Cu revealing) of the chips. The next step is to build up the redistribution layers (RDLs) from the contact pads and then mount the solder balls. Next comes the debonding of the carrier with a laser, and then the dicing of the whole reconstituted molded wafer into individual packages.

引用

页数：6

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