Design of an All-Digital, Low Power Time-to-Digital Converter in 0.18μm CMOS

被引：0
|
作者：
Pokhara, Ankur [1 ]
Agrawal, Jatin
Mishra, Biswajit
机构：
[1] VLSI, Gandhinagar 382007, India
来源：
2017 7TH INTERNATIONAL SYMPOSIUM ON EMBEDDED COMPUTING AND SYSTEM DESIGN (ISED) | 2017年
关键词：
Time-to-Digital Converter; TDC; All-Digital; Low Power; CMOS ASIC;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A full custom, all digital, low power Time-to-Digital Converter (TDC) is proposed. The proposed architecture contains a 20-bit ripple counter, an encoder, an edge detector and a Ring Delay Line (RDL). The TDC core, has an active area of 0.026mm(2) implemented in 0.18 mu m CMOS technology that achieves a resolution of 586.4ps/LSB and 201.8ps/LSB, lower power consumption of 32.5 mu W and 315.5 mu W, with the distance calculation up to 2949.4km and 1015.7km at 1V and 1.8V respectively, making it feasible for time-of-flight measurement in space applications.
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页数：5
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