High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory

被引：4

作者：

Shih, Hung-Sheng ^{[1
]}

Fang, Shang-Wei

Kang, An-Chi

King, Ya-Chin

Lin, Chrong-Jung

机构：

[1] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu 30013, Taiwan

来源：

APPLIED PHYSICS LETTERS | 2008年 / 93卷 / 21期

关键词：

CMOS memory circuits; elemental semiconductors; flash memories; silicon;

D O I：

10.1063/1.3023057

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

This work proposes a novel p-type boron-doped floating gate for n-channel split-gate flash memory. A lower program voltage, with a programming time of 7 mu s, results in five times of the conventional source-side injection programming efficiency, a 5% wider program/erase window, and more reliable endurance characteristics. Additionally, a 2 Mbit embedded flash Intellectual Property (IP) has been successfully implemented and statistically compared. The lower program voltage reduces concerns around the high-voltage decoder, the charge pump efficiency, and the array efficiency beyond 90 nm nodes. The new p-doped split-gate structure provides a very promising solution for advanced embedded split-gate flash memory beyond the 90 nm node.

引用

页数：3

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