The Sources of Erase Voltage Variability in Split-Gate Flash Memory Cell Arrays

被引：0

作者：

Tkachev, Yuri ^{[1
]}

Walls, James A. ^{[2
]}

机构：

[1] Silicon Storage Technol Inc, San Jose, CA 95134 USA

[2] Microchip Technol Inc, Tempe, AZ USA

来源：

2016 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP (IIRW) | 2016年

关键词：

Flash memory; floating gate; tunneling; capacitance; single-electron transfer;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We performed a comprehensive analysis of the voltage-to-erase (V-erase) distribution in split-gate flash memory cell arrays. It was shown that V-erase distribution is mostly determined by the tunneling voltage variations. Other factors, such as distributions of coupling ratio and FG channel parameters, have a minor effect on V-erase variability.

引用

页码：8 / 12

页数：5

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