The Sources of Erase Voltage Variability in Split-Gate Flash Memory Cell Arrays

被引：0
|
作者：
Tkachev, Yuri [1 ]
Walls, James A. [2 ]
机构：
[1] Silicon Storage Technol Inc, San Jose, CA 95134 USA
[2] Microchip Technol Inc, Tempe, AZ USA
来源：
2016 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP (IIRW) | 2016年
关键词：
Flash memory; floating gate; tunneling; capacitance; single-electron transfer;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We performed a comprehensive analysis of the voltage-to-erase (V-erase) distribution in split-gate flash memory cell arrays. It was shown that V-erase distribution is mostly determined by the tunneling voltage variations. Other factors, such as distributions of coupling ratio and FG channel parameters, have a minor effect on V-erase variability.
引用
收藏
页码：8 / 12
页数：5
相关论文
共 50 条
  • [31] Novel program versus disturb window characterization for split-gate flash cell
    Sung, HC
    Lei, TF
    Hsu, TH
    Kao, YC
    Lin, YT
    Wang, CS
    [J]. IEEE ELECTRON DEVICE LETTERS, 2005, 26 (03) : 194 - 196
  • [32] 3D Semicircular Flash Memory Cell: Novel Split-Gate Technology to Boost Bit Density
    Fujiwara, M.
    Morooka, T.
    Nagashima, S.
    Kato, T.
    Fukuda, N.
    Kariya, N.
    Ogura, T.
    Kurusu, T.
    Shimada, Y.
    Ishikawa, T.
    Arayashiki, Y.
    Hirayama, K.
    Koyama, Y.
    Kashiyama, S.
    Cai, W.
    Goki, Y.
    Sawa, K.
    Ikeno, D.
    Nishikawa, M.
    Uchiyama, Y.
    Ohtani, N.
    Arai, F.
    Kondo, M.
    [J]. 2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2019,
  • [33] The impacts of control gate voltage on the cycling endurance of split gate flash memory
    Huang, KC
    Fang, YK
    Yaung, DN
    Chen, CW
    Sung, HC
    Kuo, DS
    Wang, CS
    Liang, MS
    [J]. IEEE ELECTRON DEVICE LETTERS, 2000, 21 (07) : 359 - 361
  • [34] Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell
    Xu, Zhaozhao
    Liu, Donghua
    Hu, Jun
    Chen, Wenjie
    Qian, Wensheng
    Kong, Weiran
    Zou, Shichang
    [J]. SOLID-STATE ELECTRONICS, 2019, 152 : 46 - 52
  • [35] Performance evaluation of field-enhanced p-channel split-gate flash memory
    Chu, WT
    Lin, HH
    Wang, YH
    Hsieh, CT
    Lin, YT
    Wang, CS
    [J]. IEEE ELECTRON DEVICE LETTERS, 2005, 26 (09) : 670 - 672
  • [36] Shrinkable triple self-aligned field-enhanced split-gate flash memory
    Chu, WT
    Lin, HH
    Hsieh, CT
    Sung, HC
    Wang, YH
    Lin, YT
    Wang, CS
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2004, 51 (10) : 1667 - 1671
  • [37] Design considerations for sub-90-nm split-gate Flash-memory cells
    Saha, Samar K.
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (11) : 3049 - 3055
  • [38] Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory
    Zhao, Wei
    He, Yue-Song
    Huang, Chunchieh
    Mei, Len
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS, 2010, 49 (07) : 0741051 - 0741054
  • [39] Characterizing Radiation and Stress-Induced Degradation in an Embedded Split-Gate NOR Flash Memory
    Duncan, Adam R.
    Gadlage, Matthew J.
    Roach, Austin H.
    Kay, Matthew J.
    [J]. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2016, 63 (02) : 1276 - 1283
  • [40] Split-gate flash MLC with self-limiting programming
    Jia, James Yingbo
    Lee, Douglas
    Chen, Yueh-Hsin
    Su, Chien-Sheng
    Chen, Bomy
    Wang, S. W.
    Shieh, C. J.
    Huang, Allan
    Chu, Yi-Shin
    Yang, Jen-Sheng
    Lin, Derek
    Lin, Yung-Tao
    Wang, Chung
    [J]. 2008 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PROGRAM, 2008, : 89 - +
12345