Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems

被引：5
|
作者：
Suzuki, H [1 ]
Chang, YN [1 ]
Parhi, KK [1 ]
机构：
[1] Kawasaki Steel Corp, LSI Div, Chiba 260, Japan
来源：
PROCEEDINGS OF THE IEEE 1999 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 1999年
关键词：
D O I：
10.1109/CICC.1999.777350
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a low-power bit-serial Viterbi decoder chip with the coding rate r = 1/3 and the constraint length K = 9 (256 states). This chip is targeted for high speed convolutional decoding for next generation wireless applications. The Add-Compare-Select (ACS) units have been designed using bit-serial arithmetic and a power efficient trace-back scheme and an application-specific memory have been developed for the trace-back operation. The chip was implemented using 0.5 mu m CMOS technology and is operative at 20Mbps under 3.3V and at 2Mbps under 1.8V. The power dissipation is only 9.8mW at 2Mbps operation under 1.8V.
引用
收藏
页码：589 / 592
页数：4
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