Lookahead Legalization Based Global Placement for Heterogeneous FPGAs

With increasing size and complexity of FPGA, placement has lately become the main concern in FPGA physical design. The existing approaches use both packing and placement technique for FPGA placement separately. Unlike the existing methods, we propose a novel global placement approach for heterogeneous FPGA without undergoing packing. The focus of the work is to find the global placement of heterogeneous FPGA architecture with minimum wire length. The existing FPGA placement algorithms first consider packing the logic elements, LUTs and FFs into BLEs then place it in a target FPGA architecture. The proposed global placement approach avoids packing thereby removes the overhead of packing phase in FPGA design. The proposed method consists of (1) Clustering, (2) Fixed block (I/O) placement, (3) Window selection, (4) Placing hard blocks using lookahead legalization.(5) Placing soft blocks using lookahead legalization. The proposed algorithm is evaluated and tested on ISPD 2016 benchmark circuits. The obtained results are found at par with the results of other existing techniques with respect to total wire length.