Whitespace Redistribution For Thermal Via Insertion In 3D Stacked ICs

被引：10
|
作者：
Wong, Eric [1 ]
Lim, Sung Kyu [1 ]
机构：
[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA
来源：
2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2 | 2007年
关键词：
D O I：
10.1109/ICCD.2007.4601912
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
One of the biggest challenges in 3D stacked IC design is heat dissipation. Incorporating thermal vias is a promising method for reducing the temperatures of 3D ICs. The bonding styles between device layers impose certain restrictions to where thermal vias may be inserted. This paper presents a whitespace redistribution algorithm that takes bonding style into consideration to improve thermal via placement, which in turn reduces temperature.
引用
收藏
页码：267 / 272
页数：6
相关论文
共 50 条
  • [1] Thermal Characterization of TSV based 3D Stacked ICs
    Swarup, Sahana
    Tan, Sheldon X. -D.
    Liu, Zao
    [J]. 2012 IEEE 21ST CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, 2012, : 335 - 338
  • [2] Effectiveness of thermal redistribution layer in cooling of 3D ICs
    Wang, Fengjuan
    Li, Yue
    Yu, Ningmei
    Yang, Yuan
    [J]. INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, 2021, 34 (03)
  • [3] Thermal-aware steiner routing for 3D stacked ICs
    Pathak, Mohit
    Lim, Sung Kyu
    [J]. IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, : 205 - 211
  • [4] Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches
    Li, Dawei
    Zhang, Kaicheng
    Guliani, Akhil
    Ogrenci-Memik, Seda
    [J]. PROCEEDINGS OF THE 2017 54TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2017,
  • [5] LP based white space redistribution for thermal via planning and performance optimization in 3D ICs
    Li, Xin
    Ma, Yuchun
    Hong, Xianlong
    Dong, Sheqin
    Cong, Jason
    [J]. 2008 ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 122 - +
  • [6] Reliability Aware Through Silicon Via Planning for 3D Stacked ICs
    Shayan, Amirali
    Hu, Xiang
    Peng, He
    Cheng, Chung-Kuan
    Yu, Wenjian
    Popovich, Mikhail
    Toms, Thomas
    Chen, Xiaoming
    [J]. DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3, 2009, : 288 - +
  • [7] Placement of 3D ICs with thermal and interlayer via considerations
    Goplen, Brent
    Sapatnekar, Sachin
    [J]. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2007, : 626 - +
  • [8] Investigation on the effect of multiple parameters towards thermal management in 3D Stacked ICs
    Xiao, Chengdi
    He, Hu
    Li, Junhui
    Wang, Yan
    Zhu, Wenhui
    [J]. 2016 17TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2016, : 514 - 519
  • [9] Thermal Management and Processing Optimization for 3D Multi-layer Stacked ICs
    Lofrano, Melina
    Cherman, Vladimir
    Gerets, Carine
    Bex, Pieter
    Beyne, Eric
    [J]. 2019 25TH INTERNATIONAL WORKSHOP ON THERMAL INVESTIGATIONS OF ICS AND SYSTEMS (THERMINIC 2019), 2019,
  • [10] High Speed I/O and Thermal Effect Characterization of 3D Stacked ICs
    Groger, Moishe
    Harb, Shadi M.
    Morris, Devin
    Eisenstadt, William R.
    Puligundla, Sudeep
    [J]. 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, 2009, : 416 - +
12345