Time-To-Digital Converter with adjustable resolution using a digital Vernier Ring Oscillator

被引：0
|
作者：
Annagrebah, A. [1 ,3 ]
Bechetoille, E. [1 ]
Chanal, H. [2 ]
Mathez, H. [1 ]
Laktineh, I. [1 ,2 ,3 ]
机构：
[1] Univ Lyon 1, IPNL, CNRS, IN2P3,MICRHAU, 4 Rue E Fermi, F-69622 Villeurbanne, France
[2] Univ Blaise Pascal, LPC, CNRS, IN2P3, Aubiere, France
[3] MIND Microtec, 155 Rue Ada Byron, F-74160 Archamps, France
来源：
2018 XXXIII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS) | 2018年
关键词：
Resistive Plate Chambers (RPC); Time-to-Digital Converter (TDC); Vernier Ring Oscillator (VRO); Least Significant Bit (LSB); adjustable resolution;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we present the development of a high resolution, and low power, Time to Digital Converter (TDC) based on Vernier Ring Oscillators (VRO) made of standard XOR delay cells. The TDC is aimed at exploiting the excellent timing performance of the Resistive Plate Chambers detector (RPC). The frequency of each Ring Oscillator (RO) is adjustable thanks to a 9 bit serial register from 340 MHz to 370 MHz, allowing, theoretically an LSB selection down to one 1 ps. The core area measures 35 mu m x 75 mu m in a 130 nm CMOS technology. Under 1.2 V, the TDC consumes 2.3 mARms and 260 nA(RMS) with or without signal respectively.
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页数：4
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