MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)

被引：60

作者：

Choi, CH ^{[1
]}

Goo, JS

Oh, TY

Yu, ZP

Dutton, RW

Bayoumi, A

Cao, M

Vande Voorde, P

Vook, D

Diaz, CH

机构：

[1] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA

[2] HP Co, HP Lab, ULSI Lab, Palo Alto, CA 94303 USA

[3] Taiwan Semicond Mfg Co, Hsinchu, Taiwan

来源：

IEEE ELECTRON DEVICE LETTERS | 1999年 / 20卷 / 06期

基金：

美国国家科学基金会;

关键词：

device simulation; MOS C-V modeling; quantum mechanical corrections; SPICE; ultrathin gate oxide;

D O I：

10.1109/55.767102

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed, Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green's function solver, The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance.

引用

页码：292 / 294

页数：3

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