A 510nW 12-bit 200kS/s SAR-Assisted SAR ADC Using a Re-Switching Technique

被引：0
|
作者：
Hu, Yao-Sheng
Lin, Kai-Yue
Chen, Hsin-Shu [1 ]
机构：
[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan
来源：
2017 SYMPOSIUM ON VLSI CIRCUITS | 2017年
关键词：
low power; SAR ADC; SAR-assisted;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a 510nW 12-bit 200kS/s SAR-assisted SAR ADC in 40nm CMOS at 0.7V supply. A re-switching technique is proposed to suppress DNL spikes so that the size of DAC capacitor array can be minimized to reduce switching energy. A set of 2-way charge pump is used to decrease settling time constant and to increase sampling linearity. The prototype ADC achieves the DNL/INL performance of 0.5/0.79 LSB. Its SNDR and SFDR at Nyquist rate are 69.1dB and 81.72dB, respectively. It results in an FoMS of 182dB and an FoMW of 1.1fJ/c.-s.
引用
收藏
页码：C238 / C239
页数：2
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