Novel high-radix residue number system multipliers and adders

被引：0

作者：

Paliouras, V ^{[1
]}

Stouraitis, T ^{[1
]}

机构：

[1] Univ Patras, Dept Elect & Comp Engn, VLSI Design Lab, GR-26110 Patras, Greece

来源：

ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Radix-r module r(n) multipliers and adders are introduced in this paper. The proposed architectures are shown to require several times less area than previously reported architectures, for particular moduli of operation. The proposed architectures are preferable in an area-time sense for several cases. The complexity reduction is achieved by extending the carry-ignore property of module 2(n) operations to radices higher than 2, but not powers of 2. Detailed hardware complexity models are offered.

引用

页码：451 / 454

页数：4

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