A VLSI-Efficient Signed Magnitude Comparator for {2n-1, 2n,2n+1-1} RNS

被引:0
|
作者
Kumar, Sachin [1 ]
Chang, Chip-Hong [1 ]
机构
[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore, Singapore
关键词
RESIDUE NUMBER SYSTEM; CHINESE REMAINDER THEOREM; ALGORITHM;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Comparison of residue representations in signed Residue Number System (RNS) involves sign detection and magnitude comparison. Both are difficult operations in RNS. This paper proposes a new signed magnitude comparator for the three-moduli set RNS {2(n)-1, 2(n), 2(n+1)-1}. Two subrange identifiers are computed to simplify sign detection and accelerate the magnitude comparison without requiring full reverse conversion, large modulo adders or lookup tables. Synthesis results in 65 nm CMOS standard cell implementation show that it even outperforms the most efficient unsigned magnitude comparator for equally balanced special three-moduli set by significant margin in terms of area, delay and power consumption.
引用
收藏
页码:1966 / 1969
页数:4
相关论文
共 50 条
  • [41] Residue adder design for the modulo set {2n-1; 2n; 2n+1-1} and its application in DCT architecture for HEVC
    Kopperundevi, P.
    Prakash, M. Surya
    2022 IEEE 3RD INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS, VLSI SATA, 2022,
  • [42] AN RNS TO BINARY CONVERTER IN 2N + 1, 2N, 2N - 1 MODULI SET
    PREMKUMAR, AB
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (07): : 480 - 482
  • [43] Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {22n, 2n-1, 2n+1-1} and {22n, 2n-1, 2n-1-1}
    Molahosseini, Amir Sabbagh
    Dadkhah, Chitra
    Navi, Keivan
    Eshghi, Mohammad
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2009, E92D (09): : 1628 - 1638
  • [44] Fast sign-detection algorithm for residue number system moduli set {2n-1, 2n, 2n+1-1}
    Niras, Cheeckottu Vayalil
    Kong, Yinan
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2016, 10 (02): : 54 - 58
  • [45] New Algorithm for Signed Integer Comparison in {2n+k, 2n-1, 2n+1, 2n±1-1} and Its Efficient Hardware Implementation
    Kumar, Sachin
    Chang, Chip-Hong
    Tay, Thian Fatt
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64 (06) : 1481 - 1493
  • [46] A New Fast and Area-Efficient Adder-Based Sign Detector for RNS {2n-1, 2n, 2n+1}
    Kumar, Sachin
    Chang, Chip-Hong
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (07) : 2608 - 2612
  • [47] Efficient 1-out-of-3 Binary Signed-Digit Multiplier for the moduli set {2n-1, 2n, 2n+1}
    Saremi, Maryam
    Timarchi, Somayeh
    2013 17TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS 2013), 2013, : 123 - 124
  • [48] Efficient VLSI design for RNS reverse converter based on new moduli set (2n-1, 2n+1, 22n+1)
    Lin, Su-Hon
    Sheu, Ming-Hwa
    Lin, Jing-Shiun
    Sheu, Wen-Tsai
    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 2020 - +
  • [49] IMAGE ENCRYPTION AND DECRYPTION IN RNS DOMAIN BASED ON {2n, 22n+1-1, 2n+1, 2n-1} MODULI SET
    Reddy, P. Venkata Narasa
    Karumuri, Rajasekhar
    PROCEEDINGS OF THE 2016 INTERNATIONAL CONFERENCE ON COMMUNICATION AND ELECTRONICS SYSTEMS (ICCES), 2016, : 414 - 418
  • [50] High Precision Multiplier for RNS {2n - 1, 2n, 2n
    Ma, Shang
    Hu, Shuai
    Yang, Zeguo
    Wang, Xuesi
    Liu, Meiqing
    Hu, Jianhao
    ELECTRONICS, 2021, 10 (09)