共 50 条
- [43] Power-efficient implementation of turbo decoder in SDR system IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2004, : 119 - 122
- [44] Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures 2021 IEEE 12TH LATIN AMERICA SYMPOSIUM ON CIRCUITS AND SYSTEM (LASCAS), 2021,
- [45] A Power-Efficient Prediction Hardware Architecture for H.264 Decoding ICIEA 2010: PROCEEDINGS OF THE 5TH IEEE CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS, VOL 4, 2010, : 385 - 390
- [47] An Efficient Self Routing Scheme by Using Parent-Child Association for WSNs ADVANCES IN COMPUTATION AND INTELLIGENCE, PROCEEDINGS, 2008, 5370 : 785 - 794
- [48] An Energy-Efficient Multi-Ring-Based Routing Scheme for WSNs IEEE ACCESS, 2019, 7 : 181257 - 181272
- [49] Hardware implementation of an efficient internet protocol routing filter design Int J Comput Appl, 2008, 2 (124-127):
- [50] Power Efficient Hardware Implementation of the IF Neuron Model ADVANCED COMPUTER ARCHITECTURE, 2018, 908 : 140 - 154