CMP Process Technology in TSV Application

被引：1
|
作者：
Wang, Yuchun [1 ]
Gage, Max [1 ]
Xia, Sherry [1 ]
Tu, Wen-Chiang [1 ]
Karuppiah, Lakshmanan [1 ]
机构：
[1] Appl Mat Inc, CMP Div, Silicon Syst Grp, Sunnyvale, CA 94085 USA
来源：
CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2010 (CSTIC 2010) | 2010年 / 27卷 / 01期
关键词：
D O I：
10.1149/1.3360670
中图分类号：
O646 [电化学、电解、磁化学];
学科分类号：
081704 ;
摘要：
Through-silicon via (TSV), an emerging technology for 3D IC manufacturing, involves fabrication of vertical vias through the wafers. The two methods commonly used involve "via-first" and "via-last" process flows. While the via-last approach appears to be relatively simple with minimum impact to circuit layout, the via-first scheme may ultimately offer more benefits by enabling a higher density of I/O's. This paper describes the rapid progress made in the process integration of CMP for TSV, to offer unique advantages especially in the via-first approach where planarity is critical. In addition, with backside polishing after wafer thinning, the CMP process ensures a smooth surface finish for bonding and provide extra process knobs to correct the non-uniformity in via depths caused by preceding via etch and silicon grinding processes.
引用
收藏
页码：533 / 538
页数：6
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