Low-Error and Efficient Fixed-Width Squarer for Digital Signal Processing Applications

This paper presents a new approach of using the improved hybrid LUT-based architecture for the low-error and efficient fixed-width squarer circuits. By employing both LUT-based and simple conventional logic circuits, the good trade-off between hardware complexity and performance can be achieved. Moreover, the mathematical identity of squaring operation is exploited so that the error can be reduced significantly compared with other methods. The proposed method can also improve the speed and reduce the area of squarer circuit. The implementation and chip measurement results in 0.18-mu m CMOS technology are also presented and discussed.