Automated Diagnosis of HV/LV and Floating Gate Faults in VLSI Design

被引：0

作者：

Zhu, Qing K. ^{[1
]}

机构：

[1] Int Technol Univ, Elect Engn Dept, 355 W San Fernando St, San Jose, CA 95113 USA

来源：

PROCEEDINGS OF THE 24TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS - MIXDES 2017 | 2017年

关键词：

VLSI; Design; Multiple voltages; HV/LV; Floating gate; CAD; Tapeout;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents automated methods and CAD programs to trace the connectivity of hierarchical netlists and detect HV/LV connection or floating gate faults in VLSI design. We describe algorithms and data structures for the flattening of a hierarchical netlist as well as detecting faults in a large circuit. The paper describes experimental results and GUI capability to highlight faults in Cadence schematic window.

引用

页码：229 / 233

页数：5

共 50 条

[1] On the detectability of CMOS floating gate transistor faults
Ivanov, A
Rafiq, S
Renovell, M
Azaïs, F
Bertrand, Y
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2001, 20 (01) : 116 - 128
[2] Temporally learning floating-gate VLSI synapses
Liu, Shih-Chii
Moeckel, Rico
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 2154 - +
[3] GATE ARRAYS FOR VLSI DESIGN
FULKERSON, DE
IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY, 1982, 5 (01): : 133 - 137
[4] ON STRUCTURED GATE FOREST VLSI DESIGN
ROOS, G
LEENSTRA, J
SCHWEDERSKI, T
SPAANENBURG, L
HOEFFLINGER, B
MICROPROCESSING AND MICROPROGRAMMING, 1989, 27 (1-5): : 785 - 792
[5] GATE ARRAYS FOR VLSI DESIGN.
Fulkerson, David E.
IEEE transactions on components, hybrids, and manufacturing technology, 1981, CHMT-5 (01): : 133 - 137
[6] Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults
Higami, Yoshinobu
Takahashi, Hiroshi
Kobayashi, Shin-ya
Saluja, Kewal K.
2014 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2014, : 321 - 326
[7] Diagnosis of Parametric Faults in Linear Analog VLSI Circuits
Thakur, Sandeep
Satyanarayana, K. V. V.
Reddy, K. Chinna Malla
PROCEEDINGS OF THE 10TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND CONTROL (ISCO'16), 2016,
[8] TESTING FOR FLOATING GATE FAULTS IN CMOS COMBINATIONAL-CIRCUITS
ISMAEEL, AA
INTERNATIONAL JOURNAL OF ELECTRONICS, 1991, 71 (05) : 875 - 884
[9] Diagnosis of Parametric Faults in Linear Analog VLSI Circuits
Thakur, Sandeep
Satyanarayana, K. V. V.
Reddy, K. Chinna Malla
PROCEEDINGS OF THE 10TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND CONTROL (ISCO'16), 2016,
[10] DESIGN AND OPERATION OF A FLOATING GATE AMPLIFIER
WEN, DD
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (06) : 410 - 414

← 1 2 3 4 5 →