Two Soft-Error Mitigation Techniques for Functional units of DSP Processors

被引：0
|
作者：
Rohani, Alireza [1 ]
Kerkhoff, Hans G. [1 ]
机构：
[1] Univ Twente, Testable Design & Testing Integrated Syst Grp, CTIT, NL-7500 AE Enschede, Netherlands
来源：
2014 19TH IEEE EUROPEAN TEST SYMPOSIUM (ETS 2014) | 2014年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic has been elaborated with a fast recovery mechanism to isolate the fault-free functional units and re-execute the erroneous instruction. These techniques have been implemented on a DSP processor in order to assess the achieved fault-tolerance versus the imposed overheads.
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页数：6
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