Advanced process control of poly silicon gate critical dimensions

被引:0
|
作者
Rudolph, P. [1 ]
机构
[1] LSI Log Corp, Mfg Serv, Gresham, OR 97030 USA
关键词
APC; control; Critical Dimensions; Poly Gate CD;
D O I
10.1117/12.658860
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
The ability to control critical dimensions of structures on semiconductor devices is paramount to improving die yield and device performance. Historical methods of controlling critical dimensions include; tool matching, limiting processes to a limited tool set, and extensive monitoring. These methods have proven reasonably effective in controlling critical dimensions, but they are labor and resource intensive. The next level of factory performance is to automate corrections and drive critical dimensions to target. Use of this type of control, commonly referred to as Advanced Process Control (APC) has been a trend that is increasingly becoming the norm in our industry. This paper outlines the implementation of a controller that effectively targets Final Inspection Critical Dimensions (FICD's). This is accomplished by feeding Develop Inspection Critical Dimensions (DICD), FICD, chip code and chamber information in to a model. The controller makes use of a model to make recommendations for recipe parameters. These recipe parameters are transferred to the tool using XML protocol in an automated fashion. Offsets and disturbances are effectively adjusted for. This controller has been implemented in a production facility and has resulted in a 70% improvement in Cpk performance.
引用
收藏
页数:6
相关论文
共 50 条
  • [31] Advanced defect inspection techniques for NFET and PFET defectivity at 7nm gate poly removal process
    Tolle, Ian
    Daino, Michael
    [J]. 2018 29TH ANNUAL SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC), 2018, : 1 - 4
  • [32] Dummy Poly Silicon Gate Removal by Wet Chemical Etching
    Yang, T.
    Yin, H. X.
    Xu, Q. X.
    Zhao, C.
    Li, J. F.
    Chen, D. P.
    [J]. CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2011 (CSTIC 2011), 2011, 34 (01): : 361 - 364
  • [33] DEFECT CHARACTERIZATION OF A SILICON GATE CMOS PROCESS.
    Laneuville, Jacques
    Marcoux, Jean
    Orchard-Webb, Jon
    Comeau, Alain
    [J]. Semiconductor International, 1985, 8 (05) : 250 - 254
  • [34] Characterization of silicon surface preparation processes for advanced gate dielectrics
    Okorn-Schmidt, HF
    [J]. IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1999, 43 (03) : 351 - 365
  • [35] Advanced process control: Benefits for photolithography process control
    Gould, C
    [J]. 2002 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP: ADVANCING THE SCIENCE OF SEMICONDUCTOR MANUFACTURING EXCELLENCE, 2002, : 98 - 100
  • [36] Interfacial transition regions of gate dielectrics in advanced silicon devices
    Lucovsky, G
    Phillips, JC
    Thorpe, MF
    [J]. PROCEEDINGS OF THE 25TH INTERNATIONAL CONFERENCE ON THE PHYSICS OF SEMICONDUCTORS, PTS I AND II, 2001, 87 : 423 - 424
  • [37] JVD silicon nitride and titanium oxide as advanced gate dielectrics
    Ma, TP
    [J]. ULTRATHIN SIO2 AND HIGH-K MATERIALS FOR ULSI GATE DIELECTRICS, 1999, 567 : 73 - 81
  • [38] Advanced process control: Optimization or control
    Kern, Allan
    [J]. HYDROCARBON PROCESSING, 2010, 89 (12): : 15 - 15
  • [39] Thermally stable CVD HfOxNy advanced gate dielectrics with poly-Si gate electrode
    Choi, CH
    Rhee, SJ
    Jeon, TS
    Lu, N
    Sim, JH
    Clark, R
    Niwa, M
    Kwong, DL
    [J]. INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, 2002, : 857 - 860
  • [40] Silicon gate notching for patterning features with dimensions smaller than the resolution of the lithography
    Foucher, J
    Cunge, G
    Vallier, L
    Joubert, O
    [J]. MICROELECTRONIC ENGINEERING, 2002, 61-2 : 849 - 857