共 50 条
- [26] From Double to Triple Gate: Modeling Junctionless Nanowire Transistors [J]. 2015 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), 2015, : 5 - 8
- [28] A surface-potential-based compact model of NMOSFET gate tunneling current [J]. NANOTECH 2003, VOL 2, 2003, : 318 - 321