Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

被引：83
|
作者：
Trevisoli, Renan Doria [1 ]
Doria, Rodrigo Trevisoli [2 ]
de Souza, Michelly [2 ]
Das, Samaresh [3 ]
Ferain, Isabelle [4 ]
Pavanello, Marcelo Antonio [2 ]
机构：
[1] Univ Sao Paulo, BR-05508900 Sao Paulo, Brazil
[2] Ctr Univ FEI, BR-09850901 Sao Bernardo Do Campo, Brazil
[3] Tyndall Natl Inst, Cork, Ireland
[4] Globalfoundries, Malta, NY 12020 USA
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2012年 / 59卷 / 12期
基金：
巴西圣保罗研究基金会;
关键词：
Drain current model; junctionless nanowire transistors (JNTs); short-channel effects (SCEs); temperature dependence; DESIGN; DEVICE;
D O I：
10.1109/TED.2012.2219055
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short- channel devices down to 30 nm at different temperatures have been also used to validate the model.
引用
收藏
页码：3510 / 3518
页数：9
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