Energy-Efficient Architecture for Neural Spikes Acquisition

A new energy-efficient architecture for neural spikes acquisition implements pre-detection of neural spikes before fine conversion. The prediction is based on the low-bit coarse conversion of input data with the subsequent detection of spikes with the Teager energy operator (TEO). The example data constructed based on real neuronal data recorded from the visual cortex of an anesthetized rat shows that the systems architecture is more energy efficient as both the binary detection with further digitization and as the full conversion of all data without pre-detection. The proposed system achieves 34% energy savings compared with the full digitization with 10-bit ADC. The proposed analog memory reduces dramatically the ADCs input capacitance, and thus lowers power. Furthermore, it allows for the combination of highly linear bottom-plate sampling with an arbitrary power-efficient switching scheme. The simulation of the proposed system was performed on transistor level in 65 nm CMOS technology.