ESD in FinFET technologies: past learning and emerging challenges Invited paper

FinFET technologies were seen as a potential roadblock for providing high ESD reliable ICs due to the 3D nature of the narrow Si fins which do not allow a large current conduction before thermal failure. However, a detailed assessment of common ESD structures such as diodes and grounded gate devices, has shown that ESD reliability is not a roadblock for finFET-based products. Studying both SOI and bulk FinFETs, bulk FinFET was found to provide superior ESD performance due to the fin connection to the substrate. Focusing on sub-20-nm bulk FinFET technologies, emerging challenges are not limited to dealing with the smaller silicon volume of the fins and finer pitch, but also with the introduction of high mobility channels in the fins. The introduction of these materials can have a profound impact on the intrinsic ESD performance and must therefore be studied. In this work we will present past learning on ESD protection devices in FinFET technologies, for SOI and bulk FinFETs, TCAD methods used to analyze the ESD results, and we will present the results for non-silicon FinFET technologies which are being considered for the 14 and 10-nm CMOS nodes.