Analytical Drain Current Compact Model in the Depletion Operation Region of Short-Channel Triple-Gate Junctionless Transistors

被引：24

作者：

Oproglidis, Theodoros A. ^{[1
]}

Tsormpatzoglou, Andreas ^{[1
]}

Tassis, Dimitrios H. ^{[1
]}

Karatsori, Theano A. ^{[1
]}

Barraud, Sylvain ^{[2
]}

Ghibaudo, Gerard ^{[3
]}

Dimitriadis, Charalabos A. ^{[1
]}

机构：

[1] Aristotle Univ Thessaloniki, Thessaloniki 54124, Greece

[2] LETI CEA, F-38054 Grenoble, France

[3] IMEP LAHC Lab Minatec, F-38016 Grenoble 16, France

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2017年 / 64卷 / 01期

关键词：

Compact modeling; drain current; junctionless (JL); triple-gate (TG) transistors; VOLTAGE MODEL; CORE MODEL; TEMPERATURE; MOSFETS; BODY;

D O I：

10.1109/TED.2016.2632753

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new charge-based analytical compact model for the drain current of junctionless (JL) triple-gate MOSFETs is presented, which includes the short-channel effects, the saturation velocity overshoot, the series resistance, and the mobility degradation effects. The proposed model consists of a single analytical equation that covers the depletion operation region in which the bulk conduction determines the drain current. The model is supported by experimental measurements in JL nanowire transistors with channel length varying from 95 to 25 nm and doping concentration 2 x 10(19) cm(-3). The overall results reveal the very good accuracy of the proposed analytical compact model, making it suitable for circuit simulation tools.

引用

页码：66 / 72

页数：7

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