Design Methods for Multiple-Valued Input Address Generators

被引：0
|
作者：
Sasao, Tsutomu [1 ]
机构：
[1] Kyushu Inst Technol, Dept Comp Sci & Elect, Iizuka, Fukuoka 8208502, Japan
来源：
ISMVL 2006: 36TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC | 2006年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A multiple-valued input address generator produces a unique address given a multiple-valued input data vector This paper presents methods to realize multiple-valued input address generators by multi-level networks of p-input q-output memories. It shows a method to simplify the address generators using an auxiliary memory.
引用
收藏
页码：1 / 10
页数：10
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