FPGA implementation of the high-speed floating-point operation

In this paper, algorithms of the floating-pointmultiplication and addition are discussed. The modified Booth algorithm is founded to be an ideal algorithm Without considering the sign of the multiplier and the multiplicand, modifying the product can be eliminated and the operation speed of the multiplier is improved greatly. A low-power triple data-path architecture can be used to finish the addition.. where the prediction of the leading-one can be operated in paralleled with the subtraction of mantissa. It greatly reduces the delay of the whole floating-point adder. The floating-point operation is also implemented and synthesized in the Altera field programmable gate array (FPGA).