Design and implementation of high speed single precision floating-point radix-3 butterfly unit

被引:0
|
作者
Yu, Jiyang [1 ]
Li, Yang [1 ]
Huang, Dan [1 ]
Long, Teng [1 ]
Liu, Wei [1 ]
机构
[1] Radar Research Lab, School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China
关键词
Application programs - Precision engineering - Design for testability - Discrete Fourier transforms - Digital arithmetic - Integrated circuit design;
D O I
暂无
中图分类号
学科分类号
摘要
On the basis of analyzing existing butterfly designs, an efficient design method of pipeline single precision floating-point butterfly unit for radix-3 fast Fourier transform (FFT) is proposed. First, a simplified radix-3 butterfly model is established using the Cooley-Tukey algorithm; then, with the introducing of the constant integer multiplication, 3-point discrete Fourier transform (DFT) matrix floating-point complex multiplication is realized using finite fix-point additions. Combined with classic floating-point multiplication and addition unit, the radix-3 butterfly unit is deduced. Compared with conventional designs, the proposed design reduces floating-point operations and saves hardware resources. Simulation experiments and engineering application results show that, the proposed design method can meet the precision requirement of the system while ensuring real-time computing capability compared to other hardware or software implementation.
引用
收藏
页码:2675 / 2681
相关论文
共 50 条
  • [1] A small-area design of radix-3 butterfly unit
    Ma, Cui-Mei
    Chen, He
    Du, Qing
    [J]. Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology, 2013, 33 (10): : 1067 - 1071
  • [2] Design of a fully pipelined single-precision floating-point unit
    Li, Zhaolin
    Zhang, Xinyue
    Li, Gongqiong
    Zhou, Runde
    [J]. ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 60 - 63
  • [3] VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog
    Ushasree, G.
    Dhanabal, R.
    Sahoo, Sarat Kumar
    [J]. 2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES (ICT 2013), 2013, : 803 - 808
  • [4] High-radix implementation of IEEE floating-point addition
    Seidel, PM
    [J]. 17TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 2005, : 99 - 106
  • [5] DLX gold: Design and implementation of a DLX microprocessor with single precision Floating-Point operations
    Aguilar, John Edrian H.
    Reas, Rosario M.
    Villangca, John Benedict B.
    Villangca, B.
    Ballesil, Anastacia P.
    Reyes, Joy Alinda P.
    [J]. TENCON 2007 - 2007 IEEE REGION 10 CONFERENCE, VOLS 1-3, 2007, : 1272 - 1275
  • [6] Design and Implementation of a Reduced Floating-Point Reconfigurable Computing Unit
    Wang, Xing
    Zhang, Duo-li
    Song, Yu-kun
    Du, Gao-ming
    [J]. INTERNATIONAL CONFERENCE ON COMPUTER, NETWORK SECURITY AND COMMUNICATION ENGINEERING (CNSCE 2014), 2014, : 164 - 170
  • [7] Design, Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Multiplier
    Hara, Hiroshi
    Obata, Koji
    Park, Heejoung
    Yamanashi, Yuki
    Taketomi, Kazuhiro
    Yoshikawa, Nobuyuki
    Tanaka, Masamitsu
    Fujimaki, Akira
    Takagi, N.
    Takagi, Kazuyoshi
    Nagasawa, S.
    [J]. IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2009, 19 (03) : 657 - 660
  • [8] Design and Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Adders
    Park, Heejoung
    Yamanashi, Yuki
    Taketomi, Kazuhiro
    Yoshikawa, Nobuyuki
    Tanaka, Masamitsu
    Obata, Koji
    Ito, Yuki
    Fujimaki, Akira
    Takagi, Naofumi
    Takagi, Kazuyoshi
    Nagasawa, Shuichi
    [J]. IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2009, 19 (03) : 634 - 639
  • [9] FPGA implementation of the high-speed floating-point operation
    Ji, XS
    Wang, SR
    [J]. ICEMI 2005: Conference Proceedings of the Seventh International Conference on Electronic Measurement & Instruments, Vol 3, 2005, : 626 - 629
  • [10] High Speed and Area Efficient Single Precision Floating Point Arithmetic Unit
    Palekar, Sangeeta
    Narkhede, Nitin
    [J]. 2016 IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2016, : 1950 - 1954