VLSI architectures for median filtering with linear complexity

被引：0
|
作者：
Lu, EH
Lee, JY
Yang, YP
机构：
来源：
1996 IEEE TENCON - DIGITAL SIGNAL PROCESSING APPLICATIONS PROCEEDINGS, VOLS 1 AND 2 | 1996年
关键词：
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Two hardware architectures for median filtering with linear complexity are presented in this paper. Both of them are very suitable to implement a fitter of large window size owing to their linear hardware complexity. Also, they are suitable for high-speed signal processing because each of them can generate one filtered word in a system clock.
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页码：358 / 362
页数：5
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