Supply-Scalable High-Speed I/O Interfaces

被引:6
|
作者
Bae, Woorham [1 ,2 ]
机构
[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
[2] Ayar Labs, Santa Clara, CA 95054 USA
关键词
computer communication; dynamic voltage and frequency scaling; energy-efficient computing; high-speed interface; low power; VOLTAGE-MODE TRANSMITTER; BIDIRECTIONAL LINK; PARALLEL I/O; FRONT-END; POWER; GB/S; TRANSCEIVER; PJ/BIT; CMOS; EQUALIZATION;
D O I
10.3390/electronics9081315
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Improving the energy efficiency of computer communication is becoming more and more important as the world is creating a massive amount of data, while the interface has been a bottleneck due to the finite bandwidth of electrical wires. Introducing supply voltage scalability is expected to significantly improve the energy efficiency of communication input/output (I/O) interfaces as well as make the I/Os efficiently adapt to actual utilization. However, there are many challenges to be addressed to facilitate the realization of a true sense of supply-scalable I/O. This paper reviews the motivations, background theories, design considerations, and challenges of scalable I/Os from the viewpoint of computer architecture down to the transistor level. Thereafter, a survey of the state-of-the-arts fabricated designs is discussed.
引用
收藏
页码:1 / 21
页数:21
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