Processing Technologies for Advanced Ge Devices

With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures. (C) The Author(s) 2016. Published by ECS.