Processing Technologies for Advanced Ge Devices

被引：37

作者：

Loo, R. ^{[1
]}

Hikavyy, A. Y. ^{[1
]}

Witters, L. ^{[1
]}

Schulze, A. ^{[1
]}

Arimura, H. ^{[1
]}

Cott, D. ^{[1
]}

Mitard, J. ^{[1
]}

Porret, C. ^{[1
]}

Mertens, H. ^{[1
]}

Ryan, P. ^{[2
]}

Wall, J. ^{[2
]}

Matney, K. ^{[3
]}

Wormington, M. ^{[3
]}

Favia, P. ^{[1
]}

Richard, O. ^{[1
]}

Bender, H. ^{[1
]}

Thean, A. ^{[1
]}

Horiguchi, N. ^{[1
]}

Mocuta, D. ^{[1
]}

Collaert, N. ^{[1
]}

机构：

[1] IMEC, B-3001 Leuven, Belgium

[2] Bruker Semicond Div, Belmont Business Pk, Durham DH1 1TW, England

[3] Bruker Semicond Div, Santa Barbara, CA 93117 USA

来源：

ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY | 2017年 / 6卷 / 01期

关键词：

SHALLOW TRENCH ISOLATION; HIGH-QUALITY GE; EPITAXIAL-GROWTH; SIGE BUFFER; PERFORMANCE;

D O I：

10.1149/2.0301612jss

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures. (C) The Author(s) 2016. Published by ECS.

引用

页码：P14 / P20

页数：7

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