The hardware implementation of a generic fuzzy rule processor

被引：0
|
作者：
Qiu, B [1 ]
Woon, PL [1 ]
机构：
[1] Monash Univ, Sch Comp Sci & Software Engn, Clayton, Vic 3168, Australia
来源：
ICSP '98: 1998 FOURTH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, PROCEEDINGS, VOLS I AND II | 1998年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In this paper, the hardware design and implementation of a generic fuzzy processor is described. The processor allows the user to choose from a larger range of inference and defuzzification methods. The number of inputs and outputs was limited to 3, with a width of 8-bits for each. Rule base size and the number of inferences that can be performed per second were not a critical factor as larger and faster specifications will simply increase the end cost. Design:and simulation using Altera's Max+plus2 programmable logic development software was then conducted, and verified correct operation. The generic fuzzy processor was ultimately realised via construction using Altera FLEX 8000 FPGAs.
引用
收藏
页码：1343 / 1346
页数：4
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