共 50 条
- [1] Twin-Bit Resistive Random Access Memory in FinFET CMOS Logic Technologies [J]. 2019 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA), 2019,
- [3] An improved reconfigurable logic in resistive random access memory [J]. Integration, 2022, 87 : 169 - 175
- [5] Overview of Current Compliance Effect on Reliability of Nano Scaled Metal Oxide Resistive Random Access Memory Device [J]. 2018 4TH INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS), 2018, : 290 - 296
- [9] Gate etch process model for static random access memory bit cell and FinFET construction [J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2006, 24 (04): : 1810 - 1817
- [10] A Study of the Variability in Contact Resistive Random Access Memory by Stochastic Vacancy Model [J]. NANOSCALE RESEARCH LETTERS, 2018, 13