Challenges with Manufacturability of Package on Package (PoP)

The need to increase performance in limited space is driving packaging solutions to use the third dimension. This trend is most concrete with a package-on-package (PoP) architecture. PoP is a configuration where packaged integrated circuits (IC) are placed directly on top of each other. The interconnects are between the top package and the bottom package and the bottom package and the printed circuit board (PCB). As PoP becomes a more common solution, it is important to understand limitations in regards to manufacturability and reliability. These limitations are critical when deciding when and how to modify standard ball grid array (BGA) packaging design or process guidelines. One of the greatest challenges in assembling PoP is managing out-of-plane warpage. The direction of warpage is also not necessarily intuitive and is based on a complex interaction between the die, molding compound, and substrate and, to a lesser extent, the underfill or die attach. A critical first step is to characterize the warpage behavior of the PoP part over the expected reflow profile. The warpage of the PoP will play a key role in determining if the board bond pads should be solder mask defined (SMD) or non-solder mask defined (NSMD). Stencil design and solder materials also play critical roles. The choice of assembly materials in Design for Manufacturability (DfM) activity is just as important as board-based geometries. For example, the paste used for the interconnection should be optimized for slump and wetting characteristics, especially at elevated temperatures.