High Density PoP (Package-on-Package) and Package Stacking Development

This paper presents information concerning high density Package-on-Package (PoP) development which utilizes 0.5mm top land pitch with solder on pad (SOP). Depending on system configuration and end application PoP has inherent advantages over other packaging configurations (such as MCP or SCSP, see Figure 1). The advantages offered by PoP in terms of memory flexibility and easy testing compared to ASIC+memory die stacking have been well documented in previous papers by Yoshida et al. [1]. Thus, PoP has seen rapid adoption in consumer handheld electronics including the cellular and MP3 sectors to name a few. The demands of increased functionality coupled with footprint constraints naturally means that finer pitches need to be introduced into all packaging technologies. While this introduces its own set of challenges for traditional Chip-Scale-Packages (CSPs) the situation becomes critical in the PoP structure since finer pitches translate into less standoff between the packages. It was for this reason that the investigation of SOP covered in this paper was deemed to be necessary. The paper covers a description of the test vehicle, commercial board assembly process and board assembly materials investigated. The resulting stacking yields and Board Level Reliability (BLR) results are discussed in detail. These results show that package stacking yields are very much a factor of the materials selected for top package dipping as well as overall PoP package design. Overall stacking and BLR results conformed to high volume yield expectations.