Power Delivery Exploration Methodology Based on Constrained Optimization

被引:3
|
作者
Bairamkulov, Rassul [1 ]
Xu, Kan [1 ]
Popovich, Mikhail [2 ]
Ochoa, Juan S. [3 ]
Srinivas, Vaishnav [3 ]
Friedman, Eby G. [1 ]
机构
[1] Univ Rochester, Dept Elect & Comp Engn, 601 Elmwood Ave, Rochester, NY 14627 USA
[2] Google Inc, Platforms Dept, Mountain View, CA 94043 USA
[3] Qualcomm Corp, QCT, San Diego, CA 92121 USA
基金
美国国家科学基金会;
关键词
Optimization; Integrated circuit modeling; Measurement; System-on-chip; Integrated circuit interconnections; Load modeling; Impedance; Design methodology; design optimization; power quality; power system modeling; system-on-chip; time to market; NETWORK; IMPLEMENTATION; ENERGY;
D O I
10.1109/TCAD.2019.2925397
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The conventional power network design process requires iterative modifications to the existing power network to eliminate hot spots and to converge to target impedance parameters. At later stages in the IC design process, this procedure may require significant time and human resources due to the limited flexibility to accommodate necessary changes. Power delivery exploration during early stages of the design process may bring considerable savings to the system development effort. The number of iterations may be greatly reduced by choosing the initial parameters sufficiently close to the optimum. This paper presents a power delivery exploration framework based on constrained global optimization. The power network parameters are estimated at early stages of the development process, while considering both electrical and nonelectrical factors, such as area and cost. A Laplace transform-based circuit simulator is described that is well suited for optimization purposes due to the high computational efficiency when a large number of iterations is required. The proposed framework has been applied to the distribution of voltage domains in a large scale complex integrated system, while minimizing the cost of the decoupling capacitor placement. The optimal number of voltage rails are determined, demonstrating an approximately 40% lower on-chip area than alternative solutions.
引用
收藏
页码:1916 / 1924
页数:9
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