Glitch resistant private circuits design using HORNS

Cryptographic algorithms and their specific instantiation in computing engines leak information both through information channels and physical channels (side-channels). CMOS circuits implementing these cryptographic algorithms engines leak information through its physical attributes. The overlooked vulnerabilities in communication, cryptographic, or other system protocols and software, leak computation internal state inadvertently. These are the explicitly designed computational channels which are Turing channels. An unintended, lower barrier leakage occurs, however, through the side channels or physical channels. An actual implementation of an abstract algorithm goes through a model refinement to include the physical properties of the underlying computing machinery. Since there are no constraints placed on many of the physical attributes not visible in the algorithm specification in an abstract model, any refinement is acceptable. This is where the problem occurs. Some of these implementations reveal significant details about the private control and data flow of the underlying computation. In general there are two approaches to solve this problem. First approach is to design cryptographic algorithms which can tolerate some information leakage. Second approach is to remove the correlation between the leaked information and the secret. We propose a novel circuit design technique which uses the second approach.